1. Field of the Invention
The present invention generally relates to exchanging data on a bus between devices and, more particularly, to exchanging data between devices on a bus using a transmit buffer and assigned sequence counts.
2. Description of the Related Art
A system on a chip (SOC) generally includes one or more integrated processor cores, some type of embedded memory, such as a cache shared between the processors cores, and peripheral interfaces, such as external bus interfaces, on a single chip to form a complete (or nearly complete) system. Often SOCs communicate with other devices, such as a memory controller or graphics processing unit (GPU), by exchanging data packets over an external bus. Often, the devices will communicate over a single external bus utilizing multiple streams of data, commonly referred to as virtual channels.
According to some protocols, each data packet sent to an external device over a virtual channel is assigned a sequence count. The sequence count may be incremented for each packet, possibly rolling over to zero when a maximum sequence count is reached. Typically, the receiving device expects to receive packets with sequence counts in order and ignores packets having unexpected (out of order) sequence counts.
As a result, in such systems, there is a problem of how to recover if the two sides of the bus (receiving and transmitting devices) become out of sync as to what the next sequence count should be. This situation may arise, for example, if one of the devices is re-powered (or otherwise reset) causing their expected sequence count values to be reset. In some cases, the bus could become deadlocked because the transmitted sequence counts are not what the receive device is expecting.
As an example, a transmitting device (Chip A) may have successfully transmitted packets with sequence counts from 0 to 9 to a receiving device (Chip B). Chip B may then be reset due to some unexpected event, causing Chip B's expected sequence count to be reset to 0. Unfortunately, Chip A might only be able to send packets with sequence counts starting at 10 (having already sent packets 0-9). In this example, Chip B might never accept any more packets from Chip A, resulting in a bus deadlock.
Accordingly, what is needed is methods and systems to overcome or avoid this bus deadlock situation when transmitting and receiving device sequence counts get out of sync.